This paper proposes an enhanced replacement policy to mitigate the coherence-induced vulnerability of Cache memories by static noise margin degradation prevention. The enhancement is conducted based on the outcomes of a comprehensive study intended to investigate the causes of static noise margin degradation in the SRAM cells. The empirical analysis demonstrates that the unbalanced distribution of data blocks associated with different coherency states over lines of a Cache set can also be interpreted as a cause of the static noise margin degradation. Based on the findings, an aging-aware Cache replacement policy is presented to balance the distribution of dirty/clean data blocks over the Cache lines. To this intent, the decision tree of the Pseudo-LRU is revisited concerning the coherency state of Cache lines and the type of address conflict miss. Using the enhanced Cache, the hold and read static noise margin degradation are improved by about 9.9% and 11.5%, with less than 1.0% reduction in the Cache hit ratio and negligible area and energy overheads.

Today power consumption is considered to be one of the important issues. Therefore, its reduction plays a considerable role in developing systems. Previous studies have shown that approximately 50% of total power consumption is used in Cache memories. There is a direct relationship between power consumption and replacement quantity made in Cache. The less the number of replacements is, the less the power consumption is. In this paper, a mechanism was proposed a mechanism to reduce power consumption using full associative organization and layered replacement algorithm. In this scheme, all Cache blocks were divided into three layers. Final layer used FIFO replacement algorithm and middle layer used random replacement algorithm. Also first layer used LRU replacement algorithm. Simulation results were shown using tools written by VB language that in the proposed plan the number of replacement was less than 8-way associative using LRU replacement algorithm.